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Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme Article

Liang GENG,Ji-zhong SHEN,Cong-yuan XU

Frontiers of Information Technology & Electronic Engineering 2016, Volume 17, Issue 9, Pages 962-972 doi: 10.1631/FITEE.1500293

Abstract: A novel dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme (DIFF-CGS)

Keywords： Low power Flip-flop Implicit Clock-gating scheme Dual-edge

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Detection of solder bump defects on a flip chip using vibration analysis

Junchao LIU, Tielin SHI, Qi XIA, Guanglan LIAO

Frontiers of Mechanical Engineering 2012, Volume 7, Issue 1, Pages 29-37 doi: 10.1007/s11465-012-0314-7

Abstract:

Flip chips are widely used in microelectronics packaging owing to the high demand of integration inSolder bump defects on flip chips are difficult to detect, because the solder bumps are obscured by thewith vibration analysis is presented for detecting missing solder bumps, which is a typical defect in flipThe flip chip analytical model is revised by considering the influence of spring mass on mechanical energyThis revised model is then applied to estimate the flip chip resonance frequencies.

Keywords： flip chip defect detection ultrasonic excitation vibration analysis

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Numerical modeling of cavitation on spillway’s flip bucket

Abbas PARSAIE,Sadegh DEHDAR-BEHBAHANI,Amir Hamzeh HAGHIABI

Frontiers of Structural and Civil Engineering 2016, Volume 10, Issue 4, Pages 438-444 doi: 10.1007/s11709-016-0337-y

Abstract: paper, using Flow 3D as CFD commercial tool, the cavitation phenomenon was assessed along spillway's flip

Keywords： cavitation Index numerical simulation spillway’s flip Bucket CFD Balaroud Dam physical modeling

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Low-power, high-speed, and area-efficient sequential circuits by quantum-dot cellular automata: T-latch and counter study Research Article

Mohammad GHOLAMI, Zaman AMIRZADEH

Frontiers of Information Technology & Electronic Engineering 2023, Volume 24, Issue 3, Pages 457-469 doi: 10.1631/FITEE.2200361

Abstract:

cellular automata (QCA)%29&ck%5B%5D=abstract&ck%5B%5D=keyword'> is a new nanotechnology for the implementation of nano-sized digital circuits. This nanotechnology is remarkable in terms of speed, area, and power consumption compared to complementary metal-oxide-semiconductor (CMOS) technology and can significantly improve the design of various logic circuits. We propose a new method for implementing a in QCA technology in this paper. The proposed method uses the intrinsic features of QCA in timing and clock phases, and therefore, the proposed cell structure is less occupied and less power-consuming than existing implementation methods. In the proposed , compared to previous best designs, reductions of 6.45% in area occupation and 44.49% in power consumption were achieved. In addition, for the first time, a reset-based and a with set and reset capabilities are designed. Using the proposed , a new 3-bit is developed which reduces 2.14% cell numbers compared to the best of previous designs. Moreover, based on the 3-bit , a 4-bit is designed, which reduces 0.51% cell numbers and 4.16% cross-section area compared to previous designs. In addition, two selective s are introduced to count from 0 to 5 and from 2 to 5. Simulations were performed using and tools in coherence vector engine mode. The proposed circuits are compared with related designs in terms of delay, cell numbers, area, and leakage power.

Keywords： Quantum-dot cellular automata (QCA) Quantum-dot T-latch T-flip-flop Counter Selective counter QCADesigner